In microprocessor based system designs, the processor, one or more I/O devices, and the system memory often share a common system bus. Accordingly, communication between the system components takes place over the common system bus. There are a number of different ways in which such communications may take place. However, in each instance, the microprocessor transfers data between the various components on the system bus under the control of application programs.
The manner in which the microprocessor is allowed to handle data transfers varies with the system design. In many systems, direct memory access (DMA) controllers may be employed to significantly reduce involvement of the microprocessor in the data transfer operations and thereby increase data transfer throughput. In a DMA transfer, the microprocessor programs the DMA controller with the source and destination addresses as well as the length of the data block that is to be transferred. The microprocessor then relinquishes control of the system bus to the DMA controller, which drives the system bus and generates the control signals to perform the data transfer. The DMA controller directs the reading of the data from the source address during, for example, a first clock cycle, and directs the writing of the data to the destination address during, for example, a second clock cycle. After each word of data is transferred, the source and destination addresses are automatically incremented (or decremented), and the value for the length of the data block is decremented. The data transfer operation then is repeated for the next word. The DMA controller ceases data transfer operations in response to an underflow of the value for the length of the data block. The DMA controller generates an interrupt to the microprocessor once all data transfers of the data transaction have been completed.
Although the DMA data transfer method reduces the need for intervention of the microprocessor in various data transfer operations, it still requires the microprocessor to set up each data transaction. Further, the microprocessor must perform an interrupt service routine upon completion of each data transaction. These operations still may place a significant burden on the microprocessor.